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Lateral profiling of trapped charge in SONOS flash EEPROMs programmed using CHE injectionBHARATH KUMAR, P; NAIR, Pradeep R; SHARMA, Ravinder et al.I.E.E.E. transactions on electron devices. 2006, Vol 53, Num 4, pp 698-705, issn 0018-9383, 8 p.Article

Analysis of SRAM neutron-induced errors based on the consideration of both charge-collection and parasitic-bipolar failure modesOSADA, Kenichi; KITAI, Naoki; KAMOHARA, Shiro et al.Custom integrated circuits conference. 2004, pp 357-360, isbn 0-7803-8495-4, 1Vol, 4 p.Conference Paper

Advanced Method for Defect Characterization Using Fail Bit Analysis and Critical Area SimulationMATSUMOTO, Chizu; HAMAMURA, Yuichi; CHIDA, Takafumi et al.IEEE transactions on semiconductor manufacturing. 2011, Vol 24, Num 2, pp 151-157, issn 0894-6507, 7 p.Conference Paper

Direct Measurement of Correlation Between SRAM Noise Margin and Individual Cell Transistor Variability by Using Device Matrix Array : CHARACTERIZATION OF NANO CMOS VARIABIALITY BY SIMULATION AND MEASUREMENTSHIRAMOTO, Toshiro; SUZUKI, Makoto; XIAOWEI SONG et al.I.E.E.E. transactions on electron devices. 2011, Vol 58, Num 8, pp 2249-2256, issn 0018-9383, 8 p.Article

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A 0.13-μm, 0.78-μm² low-power four-transistor SRAM cell with a vertically stacked poly-silicon MOS and a dual-word-voltage schemeKOTABE, Akira; OSADA, Kenichi; KITAI, Naoki et al.Symposium on VLSI Circuits. 2003, pp 60-63, isbn 0-7803-8287-0, 1Vol, 4 p.Conference Paper